This specification relates to hardware circuits for performing mathematical computations.
Computational circuits can include multiple adder circuits that are used to add numerical inputs such as integers and floating-point numbers. Adder circuits can be expensive to procure and integrate into an existing computing circuit and some adder circuits are not efficiently sized for certain applications. These circuits can consume a substantial area of a circuit die but provide no advantage in computing throughput despite their large size. Adder circuits that are oversized for certain computing applications can cause inefficiencies in power consumption and utilization.
A hardware circuit can be used to implement a neural network. A neural network having multiple layers can be used to compute inferences using a computational circuit that includes multiple adder circuits. Computational circuitry of the hardware circuit can also represent a computation unit that is used to perform neural network computations for a given layer. For example, given an input, the neural network can compute an inference for the input by performing dot product operations using one or more of the multiple adders in a computation unit of the hardware circuit.